In very large scale integration (VLSI) technology, thermal stable and moisture resistant silicon dioxide is widely used as an inter-layer dielectric material for metal interconnects. The metal interconnects are often made of aluminum. However, with shrunk device components and increased degree of integration, the number of interconnects has continually increased. Consequently, parasitic effects generated by the resistor (R) and capacitor (C) in the interconnect structure can cause serious RC delay.
Therefore, to lower resistance of conducting lines, copper has been widely used in the interconnect structure to replace aluminum as an interconnect material, due to a high melting point, a low resistivity, and a high resistance to electron migration. To lower the parasitic capacitance, materials with low dielectric constant (i.e., low-k) are used to reduce the parasitic capacitance.
FIG. 1 depicts an existing method for forming a porous low-k dielectric layer. As shown, a substrate 100 is provided and placed in a reaction chamber (not shown). Two main reaction gases, diethoxymethylsilane (DEMS) 101 and terpinene (ATRP) 102, are introduced into the reaction chamber. A temperature in the reaction chamber is about 300° C. After a period of time, a dielectric layer 103 can be formed on the surface of the substrate 100. Then, referring to FIGS. 3-4, the dielectric layer 103 is cured by UV light 104 to form a porous low-k dielectric layer 105.
However, existing methods for forming the porous low-k dielectric layer include complicated processes with low production efficiency.